The present invention relates to a unit for processing electrical information-carrying signals, and then particularly, but not exclusively, to a unit which is adapted to process and/or handle signals which occur as bit positions in digital signals.
The invention is expected to find particular use in the telecommunications field, and then within signal systems in which information is presented in data packets or data cells, such as in an ATM system.
The signal processing unit according to the invention is based on the assumption that the bit positions of each incoming signal to be dealt with are time-controlled in relation to a first system-control clock signal or to system-control clock pulses which together form the clock signal, and wherein the bit positions of each signal outgoing from the unit are time-related precisely to the first system-control clock signal.
It will be understood from this that with regard to a system-control clock signal, the transmitted data signals must be synchronized exactly to the clock-signal clock pulses. Although it is unnecessary for the received signals to have this exact synchronism, these signals must nevertheless be related to the clock signal pulses and therewith related to the system.
Naturally, at least one or some, or perhaps all of the signal processing procedures require the presence of the clock pulses of a clock signal.
The present invention finds particularly suitable application when the clock signal and/or its clock pulses have a frequency above 100 Mb/s or Mhz.
Many different kinds of signal processing units of the afore-defined general kind and for the aforesaid technical field are known to the art.
Although it is expected that the present invention will find particular use in systems in which the signals are comprised of data packets, the following description will be made with reference to a multiplexing or demultiplexing unit adapted for data packets, for the sake of simplification.
A multiplexing/demultiplexing unit of this kind may be included in terminating units for switches or selectors that can be used in telecommunications systems.
When utilizing the multiplexing function of such a unit, received data cells that occur simultaneously on a number of lines at a first rate are series-parallel converted by control logic, parallel-stored in a memory and outputted at a second, higher rate through the medium of buffer circuits, parallel-series converters and clock pulse converters. Rate changes between standardized transmission rates, 155 Mb/s and 622 Mb/s are not unusual.
When practicing known techniques, received signals are processed internally within units of this kind, these signals being constantly adjusted time-wise so as to be related with sufficient accuracy to the clock pulses of a system-control clock signal generated in a master clock.
A constantly recurring problem when processing signals within these units is that the bit positions of the signals must always lie time-wise in phase with the clock pulses of the clock signal, and that there often occurs between these bit positions minor time discrepancies which must be adjusted and corrected through the medium of control circuits.
It is known to create through the medium of separate circuits conditions whereby the bit positions of the data signals can be shifted (delayed) slightly in time towards exact synchronism with the system-control clock pulses, prior to, during and/or subsequent to the internal signal processing procedure.
It is also known that this adaptation of the bit positions with a time-wise shift of the time positions of the bit positions towards exact synchronism requires comprehensive construction work.
Furthermore, a synchronizing circuit of this type which, with the aid of adaptable bit-position delay means, is intended to achieve synchronization between the bit positions and the synchronizing pulses is energy demanding and generates high power and therewith takes up a large silicon surface area of a silicon carrier.
The principle on which these procedures are based places narrow limits on the extent to which the individual bit positions can be corrected and are laden with difficulties in following varying delays in the time sections of the bit positions.